The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Oct. 26, 2023
Applicant:

Monolithic 3d Inc., Klamath Falls, OR (US);

Inventors:

Zvi Or-Bach, Haifa, IL;

Jin-Woo Han, San Jose, CA (US);

Eli Lusky, Ramat-Gan, IL;

Assignee:

Monolithic 3D Inc., Klamath Falls, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.


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