The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2024
Filed:
Feb. 22, 2019
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventor:
Jau-Yi Wu, Hsinchu County, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H10B 63/00 (2023.01); H10B 61/00 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01); H01F 10/32 (2006.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10B 63/24 (2023.02); H10B 61/10 (2023.02); H10N 50/01 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/231 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H01F 10/3254 (2013.01); H10N 50/80 (2023.02); H10N 50/85 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02);
Abstract
A method for manufacturing a memory device includes forming a dielectric layer over a substrate. A bottom electrode via opening is formed in the dielectric layer. A bottom electrode is formed in the bottom electrode via opening. The bottom electrode is etched back. A selector is formed in the bottom electrode via opening and over the bottom electrode. A memory layer is formed over the selector. A top electrode is formed over the memory layer.