The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2024
Filed:
May. 08, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kuan-Yueh Shen, Portland, OR (US);
Nasser Kurd, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/081 (2006.01); H03L 7/07 (2006.01); H03K 5/156 (2006.01); H03L 7/087 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0814 (2013.01); H03K 5/1565 (2013.01); H03L 7/07 (2013.01); H03L 7/087 (2013.01); H03L 7/0818 (2013.01);
Abstract
A multi-feedback circuit that compares a duty cycle corrected reference clock f, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fwith approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.