The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

May. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shu Ling Liao, Taichung, TW;

Chung-Chi Ko, Nantou, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823864 (2013.01); H01L 21/28123 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/4983 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.


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