The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Nov. 18, 2022
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Suresh Rajan, San Jose, CA (US);

Abhijit M. Abhyankar, Sunnyvale, CA (US);

Ravindranath Kollipara, Palo Alto, CA (US);

David A. Secker, San Jose, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0635 (2013.01); G06F 3/0613 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 13/1678 (2013.01); Y02D 10/00 (2018.01);
Abstract

Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.


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