The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jun. 03, 2022
Applicant:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Inventors:

Chwei-Po Chew, San Jose, CA (US);

Bradley A. Sharpe-Geisler, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/24 (2006.01); G06F 1/28 (2006.01); H03K 17/22 (2006.01);
U.S. Cl.
CPC ...
G06F 1/24 (2013.01); G06F 1/28 (2013.01); H03K 17/223 (2013.01);
Abstract

Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.


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