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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11906569 B1

PDFFull Text
Date of Patent:
Feb. 20, 2024

Filed:

Nov. 05, 2021

Semiconductor wafer evaluation apparatus and semiconductor wafer manufacturing method

Applicant:

Showa Denko K.k., Tokyo, JP;

Inventors:

Koichi Murata, Yokosuka, JP;

Isaho Kamata, Yokosuka, JP;

Hidekazu Tsuchida, Yokosuka, JP;

Akira Miyasaka, Chickibu, JP;

Assignee:

SHOWA DENKO K.K., Tokyo, JP;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Jermele M Hollington

Assistant Examiner:

Courtney G McDonnough

Int. Cl.
CPC ...
G01R 1/06 (2006.01); G01R 31/26 (2020.01); H01L 21/66 (2006.01); G01R 1/067 (2006.01); C30B 29/36 (2006.01); C23C 16/32 (2006.01); C23C 16/52 (2006.01); C30B 25/16 (2006.01); G01R 31/265 (2006.01); C30B 35/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2601 (2013.01); C23C 16/325 (2013.01); C23C 16/52 (2013.01); C30B 25/16 (2013.01); C30B 29/36 (2013.01); G01R 1/06783 (2013.01); G01R 31/2648 (2013.01); G01R 31/2656 (2013.01); H01L 22/20 (2013.01); C30B 35/00 (2013.01);
Abstract

A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.

Find Patent Forward Citations

Murata, Koichi. (2024). Semiconductor wafer evaluation apparatus and semiconductor wafer manufacturing method (U.S. Patent No. 11906569). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11906569

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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