The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Apr. 30, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Junjing Bao, San Diego, CA (US);

Haining Yang, San Diego, CA (US);

Youseok Suh, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66515 (2013.01); H01L 21/0217 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 23/535 (2013.01); H01L 29/41775 (2013.01);
Abstract

In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.


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