The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Sep. 28, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Shuangshuang Wu, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/91 (2013.01); H01L 28/92 (2013.01); H10B 12/033 (2023.02); H10B 12/09 (2023.02);
Abstract

A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate includes an array region and a peripheral region adjacent to each other, and the array region includes a buffer region connected with the peripheral region; a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, are formed on the substrate; a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, is formed in the buffer region; the third dielectric layer is removed through a wet etching process; and the second supporting layer in the peripheral region is etched after the third dielectric layer is removed.


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Wu, Shuangshuang. (2024). Semiconductor structure and method for manufacturing semiconductor structure (U.S. Patent No. 11901405). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11901405

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