The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

May. 26, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventor:

Jason Guo, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G05F 3/02 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G05F 3/02 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 5/145 (2013.01); G11C 8/08 (2013.01); G11C 2211/5631 (2013.01);
Abstract

A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.


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