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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11900665 B1

PDFFull Text
Date of Patent:
Feb. 13, 2024

Filed:

Jul. 25, 2023

Graphics neural network processor, method, and system

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Barnan Das, Newark, CA (US);

Mayuresh M. Varerkar, Folsom, CA (US);

Narayan Biswal, Folsom, CA (US);

Stanley J. Baran, Chandler, AZ (US);

Gokcen Cilingir, San Jose, CA (US);

Nilesh V. Shah, Folsom, CA (US);

Archie Sharma, Folsom, CA (US);

Sherine Abdelhak, Beaverton, OR (US);

Praneetha Kotha, Atlanta, GA (US);

Neelay Pandit, Beaverton, OR (US);

John C. Weast, Portland, OR (US);

Mike B. Macpherson, Portland, OR (US);

Dukhwan Kim, Mountain View, CA (US);

Linda L. Hurd, Cool, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Joydeep Ray, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Jaffery Watson Mendonsa & Hamilton LLP

Primary Examiner:

Kenny A Cese

Int. Cl.
CPC ...
G06V 10/82 (2022.01); G06V 40/10 (2022.01); G06V 10/94 (2022.01); G06V 10/764 (2022.01); G06V 40/20 (2022.01); G06F 16/783 (2019.01); G06F 16/583 (2019.01); G06F 18/2413 (2023.01); G06V 10/10 (2022.01);
U.S. Cl.
CPC ...
G06V 10/82 (2022.01); G06F 16/5838 (2019.01); G06F 16/784 (2019.01); G06F 18/24143 (2023.01); G06V 10/764 (2022.01); G06V 10/955 (2022.01); G06V 40/10 (2022.01); G06V 40/103 (2022.01); G06V 40/23 (2022.01);
Abstract

A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

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