The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Jul. 29, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Joshua Randall, Austin, TX (US);

Alejandro Rico Carro, Austin, TX (US);

Dam Sunwoo, Austin, TX (US);

Saurabh Pijuskumar Sinha, Schertz, TX (US);

Jamshed Jalal, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 12/084 (2016.01); H04L 45/42 (2022.01); H04L 49/109 (2022.01); G06F 12/0813 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/084 (2013.01); G06F 12/0813 (2013.01); G06F 12/0893 (2013.01); H04L 45/42 (2013.01); H04L 49/109 (2013.01);
Abstract

Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.


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