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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11894425 B1

PDFFull Text
Date of Patent:
Feb. 06, 2024

Filed:

Feb. 06, 2023

Semiconductor arrangement and method of manufacture

Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Yun-Chi Wu, Tainan, TW;

Tsung-Yu Yang, Tainan, TW;

Cheng-Bo Shu, Tainan, TW;

Chien Hung Liu, Hsinchu County, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Attorney:

COOPER LEGAL GROUP, LLC

Primary Examiner:

J E Schoenholtz

Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 21/3213 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/02 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/0276 (2013.01); H01L 21/02164 (2013.01); H01L 21/266 (2013.01); H01L 21/2652 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 27/092 (2013.01); H01L 29/401 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01); H10B 10/12 (2023.02);
Abstract

A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

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