The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

May. 24, 2022
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Jung-Hsing Chien, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/7682 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 29/41725 (2013.01); H01L 29/4236 (2013.01); H01L 2224/0217 (2013.01); H01L 2224/0219 (2013.01); H01L 2224/02181 (2013.01); H01L 2224/02185 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05007 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/10135 (2013.01);
Abstract

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.


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