The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Apr. 12, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Michael Grobis, Campbell, CA (US);

James W. Reiner, Palo Alto, CA (US);

Michael Nicolas Albert Tran, San Jose, CA (US);

Juan P. Saenz, Menlo Park, CA (US);

Gerrit Jan Hemink, Eindhoven, NL;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 7/20 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
G11C 11/1659 (2013.01); G11C 7/20 (2013.01); G11C 13/003 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1443 (2013.01);
Abstract

In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.


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