The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Mar. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Cheng Ching, Hsinchu County, TW;

Ka-Hing Fung, Hsinchu County, TW;

Chih-Sheng Chang, Hsinchu, TW;

Zhiqiang Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/02532 (2013.01); H01L 21/0332 (2013.01); H01L 21/324 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0924 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 29/517 (2013.01);
Abstract

A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.


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