The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Sep. 25, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Iosif Gasparakis, Hillsboro, OR (US);

Malini Bhandaru, San Jose, CA (US);

Ranganath Sunku, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 41/5003 (2022.01); G06F 12/084 (2016.01); G06F 9/455 (2018.01); H04L 43/08 (2022.01); H04L 47/70 (2022.01); G06F 12/0864 (2016.01); H04L 67/568 (2022.01);
U.S. Cl.
CPC ...
H04L 41/5003 (2013.01); G06F 9/45558 (2013.01); G06F 12/084 (2013.01); G06F 12/0864 (2013.01); H04L 43/08 (2013.01); H04L 47/82 (2013.01); H04L 67/568 (2022.05); G06F 2009/4557 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45595 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/154 (2013.01); G06F 2212/6032 (2013.04);
Abstract

Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.


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