The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2024
Filed:
Apr. 26, 2022
Applicant:
Amkor Technology Japan, Inc., Usuki, JP;
Inventor:
Masafumi Suzuhara, Yokohama, JP;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/50 (2006.01); H01L 21/288 (2006.01); H01L 21/52 (2006.01); H01L 21/76 (2006.01); H01L 21/78 (2006.01); H01L 23/28 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49524 (2013.01); H01L 21/4825 (2013.01); H01L 21/4842 (2013.01); H01L 21/56 (2013.01); H01L 23/3142 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49565 (2013.01); H01L 23/49582 (2013.01); H01L 23/3107 (2013.01);
Abstract
A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.