The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Feb. 18, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Vamsi Rayaprolu, San Jose, CA (US);

Ashutosh Malshe, Fremont, CA (US);

Gary Besinga, Boise, ID (US);

Roy Leonard, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); G11C 16/26 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3495 (2013.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01);
Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.


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