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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11887667 B1

PDFFull Text
Date of Patent:
Jan. 30, 2024

Filed:

Aug. 09, 2021

Select gate transistor with segmented channel fin

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Darwin A. Clampitt, Wilder, ID (US);

Albert Fayrushin, Boise, ID (US);

Matthew J. King, Boise, ID (US);

Madison D Drake, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Schwegman Lundberg & Woessner, P.A.

Primary Examiner:

Matthew L Reames

Assistant Examiner:

Fakeha Sehar

Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

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