The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2024
Filed:
Nov. 09, 2021
Sambanova Systems, Inc., Palo Alto, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Emre Ali Burhan, Sunnyvale, CA (US);
Manish K. Shah, Austin, TX (US);
Raghu Prabhakar, San Jose, CA (US);
Ravinder Kumar, Fremont, CA (US);
Arnav Goel, San Jose, CA (US);
Ranen Chatterjee, Fremont, CA (US);
Gregory Frederick Grohoski, Bee Cave, TX (US);
Kin Hing Leung, Cupertino, CA (US);
Dawei Huang, San Diego, CA (US);
Manoj Unnikrishnan, Saratoga, CA (US);
Martin Russell Raumann, San Leandro, CA (US);
Bandish B. Shah, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.