The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2024
Filed:
Nov. 09, 2021
Sambanova Systems, Inc., Palo Alto, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Emre Ali Burhan, Sunnyvale, CA (US);
Manish K. Shah, Austin, TX (US);
Raghu Prabhakar, San Jose, CA (US);
Ravinder Kumar, Fremont, CA (US);
Arnav Goel, San Jose, CA (US);
Ranen Chatterjee, Fremont, CA (US);
Gregory Frederick Grohoski, Bee Cave, TX (US);
Kin Hing Leung, Cupertino, CA (US);
Dawei Huang, San Diego, CA (US);
Manoj Unnikrishnan, Saratoga, CA (US);
Martin Russell Raumann, San Leandro, CA (US);
Bandish B. Shah, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.