The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Dec. 26, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Jonathan D. Pearce, Hillsboro, OR (US);

Dan Baum, Haifa, IL;

Guei-Yuan Lueh, San Jose, CA (US);

Michael Espig, Newberg, OR (US);

Christopher J. Hughes, Santa Clara, CA (US);

Raanan Sade, Kibutz Sarid, IL;

Robert Valentine, Kiryat Tivon, IL;

Mark J. Charney, Lexington, MA (US);

Alexander F. Heinecke, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Int. Cl.
CPC ...
G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 9/3001 (2013.01); G06F 9/30018 (2013.01); G06F 9/30038 (2023.08);
Abstract

Disclosed embodiments relate to systems and methods for performing nibble-sized operations on matrix elements. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction the fetched instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode to indicate the processor is to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix. The exemplary processor includes execution circuitry to execute the decoded instruction as per the opcode.


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