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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11881442 B1

PDFFull Text
Date of Patent:
Jan. 23, 2024

Filed:

Jul. 02, 2020

Soi active transfer board for three-dimensional packaging and preparation method thereof

Applicants:

Fudan University, Shanghai, CN;

Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd, Shanghai, CN;

Inventors:

Bao Zhu, Shanghai, CN;

Lin Chen, Shanghai, CN;

Qingqing Sun, Shanghai, CN;

Wei Zhang, Shanghai, CN;

Assignee:

Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd., Shanghai, CN;

Attorney:

Thomas E. Lees, LLC

Primary Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/775 (2006.01); H01L 27/088 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76841 (2013.01); H01L 21/76898 (2013.01); H01L 21/823871 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01);
Abstract

Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.

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