The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

May. 25, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Paolo Fantini, Vimercate, IT;

Corrado Villa, Sovico, IT;

Stefan Frederik Schippers, Peschiera del Garda, IT;

Efrem Bolandrina, Fiorano al Serio, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H10B 63/00 (2023.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H10B 63/34 (2023.02); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); H10B 63/845 (2023.02); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01);
Abstract

The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.


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