The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2024
Filed:
May. 15, 2020
Sumitomo Electric Industries, Ltd., Osaka, JP;
Sumitomo Electric Printed Circuits, Inc., Koka, JP;
Junichi Motomura, Osaka, JP;
Koji Nitta, Osaka, JP;
Shoichiro Sakai, Osaka, JP;
Mari Sogabe, Osaka, JP;
Mitsutaka Tsubokura, Osaka, JP;
Akira Tsuchiko, Osaka, JP;
Masashi Iwamoto, Koka, JP;
SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka, JP;
SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., Koka, JP;
Abstract
The printed circuit board includes, a first conductive layer including copper foil, an insulating base layer, and a second conductive layer including copper foil in this order, and includes a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction. The via-hole laminate has an electroless copper plating layer stacked on the connection hole and an electrolytic copper plating layer stacked on the electroless copper plating layer. The copper foil has copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of 10 μm or more. The electroless copper plating layer includes palladium and tin, and an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 μg/cmor more and 0.40 μg/cmor less.