The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Apr. 26, 2022
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Hajee Mohammed Shuaeb Fazeel, Bengaluru, IN;

Jitendra Kumar Yadav, Bengaluru, IN;

Thomas Evan Wilson, Laurel, MD (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/134 (2014.01); H03L 7/081 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/134 (2014.07); H03L 7/0818 (2013.01); H03K 2005/00195 (2013.01);
Abstract

The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.


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