The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2024

Filed:

Jun. 25, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Abinash Roy, San Diego, CA (US);

Lohith Kumar Vemula, San Diego, CA (US);

Bharani Chava, Cork City, IE;

Jonghae Kim, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01G 4/232 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 21/4803 (2013.01); H01L 21/4857 (2013.01); H01L 23/13 (2013.01); H01L 23/49822 (2013.01); H01L 23/642 (2013.01); H01G 4/232 (2013.01);
Abstract

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.


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