The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2024
Filed:
Jan. 04, 2021
Applicant:
Silicon Storage Technology, Inc., San Jose, CA (US);
Inventors:
Hieu Van Tran, San Jose, CA (US);
Thuan Vu, San Jose, CA (US);
Stanley Hong, San Jose, CA (US);
Stephen Trinh, San Jose, CA (US);
Anh Ly, San Jose, CA (US);
Nhan Do, Saratoga, CA (US);
Mark Reiten, Alamo, CA (US);
Assignee:
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 16/08 (2006.01); G11C 11/54 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 11/54 (2013.01); G11C 16/24 (2013.01); G11C 2216/04 (2013.01);
Abstract
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.