Apparatuses, methods, and systems for instructions to multiply floating-point values of about zero

Abstract

Systems, methods, and apparatuses relating to instructions to multiply floating-point values of about zero are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first floating-point number, a second field that identifies a second floating-point number, and a third field that indicates an about zero threshold; and an execution circuit to execute the decoded single instruction to: cause a first comparison of an exponent of the first floating-point number to the about zero threshold, cause a second comparison of an exponent of the second floating-point number to the about zero threshold, provide as a resultant of the single instruction a value of zero when the first comparison indicates the exponent of the first floating-point number does not exceed the about zero threshold, provide as the resultant of the single instruction the value of zero when the second comparison indicates the exponent of the second floating-point number does not exceed the about zero threshold, and provide as the resultant of the single instruction a product of a multiplication of the first floating-point number and the second floating-point number when the first comparison indicates the exponent of the first floating-point number exceeds the about zero threshold and the second comparison indicates the exponent of the second floating-point number exceeds the about zero threshold.