The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2024
Filed:
Feb. 13, 2020
Intel Corporation, Santa Clara, CA (US);
Amit K Srivastava, Folsom, CA (US);
Majid Shushtarian, Pleasanton, CA (US);
Anand K Enamandram, Folsom, CA (US);
Jared W Havican, Folsom, CA (US);
Jeffrey A Pihlman, Steilacoom, WA (US);
Michael J Karas, Beaverton, OR (US);
Ramamurthy Krithivas, Chandler, AZ (US);
Christine Watnik, Union City, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH. The multi-socket platforms include a platform with a bootable CPU coupled to one or more non-legacy CPUs and employing multiple IO-expanders and platform with a legacy CPU coupled to one or more non-legacy CPUs and coupled to a legacy PCH, and further including one or more PCHs coupled to the non-legacy CPU(s) implemented as IO-expanders.