The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Jun. 14, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

S M Istiaque Hossain, Boise, ID (US);

Christopher J. Larsen, Boise, ID (US);

Anilkumar Chandolu, Boise, ID (US);

Wesley O. McKinsey, Nampa, ID (US);

Tom J. John, Boise, ID (US);

Arun Kumar Dhayalan, Boise, ID (US);

Prakash Rau Mokhna Rau, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/35 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01);
U.S. Cl.
CPC ...
H10B 43/35 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02);
Abstract

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.


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