The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

May. 13, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Manasi Deval, Portland, OR (US);

Gregory Bowers, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 9/40 (2022.01); H04L 9/08 (2006.01); H04L 69/324 (2022.01); H04L 69/16 (2022.01); H04L 69/321 (2022.01); H04L 69/164 (2022.01);
U.S. Cl.
CPC ...
H04L 63/0428 (2013.01); H04L 9/088 (2013.01); H04L 63/06 (2013.01); H04L 69/161 (2013.01); H04L 69/164 (2013.01); H04L 69/321 (2013.01); H04L 69/324 (2013.01);
Abstract

Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.


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