The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Jul. 02, 2020
Applicants:

Fudan University, Shanghai, CN;

Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd, Shanghai, CN;

Inventors:

Wei Zhang, Shanghai, CN;

Ziyu Liu, Shanghai, CN;

Lin Chen, Shanghai, CN;

Qingqing Sun, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 27/01 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 27/01 (2013.01); H01L 24/05 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01);
Abstract

The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method, The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer; and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor, The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.


Find Patent Forward Citations

Loading…