The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2024
Filed:
Dec. 30, 2021
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Tomohiko Yamagishi, Kanagawa, JP;
Seiji Narui, Kanagawa, JP;
Kiyoshi Nakai, Tokyo, JP;
Takamasa Suzuki, Tokyo, JP;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); G11C 29/42 (2006.01); G11C 11/4074 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/4074 (2013.01); G11C 11/4093 (2013.01); G11C 29/42 (2013.01);
Abstract
Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.