The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

Nov. 18, 2020
Applicant:

Groq, Inc., Mountain View, CA (US);

Inventors:

Brian Lee Kurtz, Southlake, TX (US);

Dinesh Maheshwari, Fremont, CA (US);

James David Sprach, Monte Sereno, CA (US);

Assignee:

Groq, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 5/01 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 5/01 (2013.01); G06F 9/3802 (2013.01); G06F 9/3856 (2023.08); G06F 9/3885 (2013.01);
Abstract

A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions. The processed instructions are dispatched to columns of the computational array via a plurality of instruction queues, wherein an instruction vector of instructions is shifted between adjacent instruction queues in a first direction, and dispatches instructions to the computational elements in a second direction.


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