The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2024
Filed:
Nov. 28, 2022
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Antonino Mondello, Messina, IT;
Carmelo Condemi, San Giovanni la Punta, IT;
Francesco Tomaiuolo, Acireale, IT;
Tommaso Zerilli, Mascalucia, IT;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 12/14 (2006.01); G06F 21/60 (2013.01); H04L 9/32 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 21/602 (2013.01); G06F 11/1068 (2013.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); H04L 9/3242 (2013.01); H04L 9/3278 (2013.01);
Abstract
An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.