The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

May. 25, 2022
Applicants:

Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd., Qinhuangdao, CN;

Avary Holding (Shenzhen) Co., Limited., Shenzhen, CN;

Inventors:

Chih-Chieh Fu, New Taipei, TW;

Yuan-Yu Lin, New Taipei, TW;

Ze-Jie Li, Qinhuangdao, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/42 (2006.01); H05K 3/46 (2006.01); H05K 1/18 (2006.01); H05K 1/11 (2006.01); H05K 3/34 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H05K 3/429 (2013.01); H05K 1/116 (2013.01); H05K 1/181 (2013.01); H05K 1/183 (2013.01); H05K 3/3494 (2013.01); H05K 3/4644 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3512 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A method for manufacturing a fan-out chip packaging structure with decreased use of a crack-inducing hot-soldering process includes a first carrier plate with first and a second outer wiring layers. Two first conductive posts are formed on the first outer wiring layer, one end of each post is electrically connected to the first outer wiring layer. A receiving groove is formed between first conductive posts, and a sidewall of each post is surrounded by a first insulating layer. An embedded component is laid in the receiving groove and a second carrier plate is formed on the first insulating layer, wherein the second carrier plate carries third and fourth outer wiring layers. A first outer component is connected to the second outer wiring layer, and a second outer component is connected to the fourth outer wiring layer.


Find Patent Forward Citations

Loading…