The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Apr. 22, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron D. Lilak, Beaverton, OR (US);

Rishabh Mehandru, Portland, OR (US);

Cory Weber, Hillsboro, OR (US);

Willy Rachmady, Beaverton, OR (US);

Varun Mishra, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/0217 (2013.01); H01L 21/02293 (2013.01); H01L 21/02532 (2013.01); H01L 21/823431 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1091 (2013.01); H01L 29/165 (2013.01); H01L 29/42368 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/78696 (2013.01);
Abstract

Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.


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