The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Jun. 16, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kun-Yuan Wu, Kaohsiung, TW;

Wei-Jen Wang, Tainan, TW;

Chien-Fu Chen, Miaoli County, TW;

Chen-Hsien Hsu, Hsinchu County, TW;

Chien-Hung Chen, Taipei, TW;

Chun-Hsien Lin, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H03K 19/20 (2013.01);
Abstract

An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.


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