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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11862472 B1

PDFFull Text
Date of Patent:
Jan. 02, 2024

Filed:

Aug. 23, 2022

Methods for polishing dielectric layer in forming semiconductor device

Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Xiaohong Zhou, Wuhan, CN;

Assignee:

YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;

Attorney:

BAYES PLLC

Primary Examiner:

Jiong-Ping Lu

Int. Cl.
CPC ...
H01L 21/3105 (2006.01); B24B 1/00 (2006.01); B24B 37/04 (2012.01); C09G 1/00 (2006.01); C09G 1/02 (2006.01); C09G 1/04 (2006.01); C09G 1/06 (2006.01); C09K 3/14 (2006.01); C09K 13/06 (2006.01); H01L 21/306 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31053 (2013.01); B24B 1/00 (2013.01); B24B 37/044 (2013.01); C09G 1/00 (2013.01); C09G 1/02 (2013.01); C09G 1/04 (2013.01); C09G 1/06 (2013.01); C09K 3/1454 (2013.01); C09K 13/06 (2013.01); H01L 21/30625 (2013.01); H01L 21/3212 (2013.01);
Abstract

Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. The methods include forming a stack structure in a staircase region and a core array region, the stack structure including a staircase structure in the staircase region; forming a dielectric layer over the staircase region and a peripheral region outside the stack structure; and polishing the dielectric layer using an auto-stop slurry containing a ceria-based abrasive.

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Zhou, Xiaohong. (2024). Methods for polishing dielectric layer in forming semiconductor device (U.S. Patent No. 11862472). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11862472

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