The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Feb. 15, 2020
Applicant:

Tohoku University, Sendai, JP;

Inventors:

Masanori Natsui, Sendai, JP;

Daisuke Suzuki, Sendai, JP;

Akira Tamakoshi, Sendai, JP;

Takahiro Hanyu, Sendai, JP;

Tetsuo Endoh, Sendai, JP;

Hideo Ohno, Sendai, JP;

Assignee:

TOHOKU UNIVERSITY, Sendai, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G06F 17/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G06F 17/142 (2013.01); G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01);
Abstract

The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.


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