Device interface board supporting devices with multiple different standards to interface with the same socket

Abstract

An automated test equipment (ATE) apparatus comprising a tester processor operable to generate commands and data for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a field programmable gate array (FPGA) communicatively coupled to the tester processor, wherein the FPGA comprises routing logic operable to route signals associated with the commands and data in the FPGA based on a type of the device under test (DUT). Further, the ATE comprises a connector module communicatively coupled to the FPGA comprising a socket to which the DUT connects and further comprising circuitry for routing the signals to a set of pins on the DUT, wherein the set of pins are associated with a first type of DUT. The circuitry can support multiple different DUT types having a common form factor but different pinout assignments.