The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

May. 10, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Yu Ling, Hsinchu, TW;

Katherine H. Chiang, New Taipei, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); G11C 11/22 (2006.01); H10B 51/10 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); G11C 11/223 (2013.01); H10B 51/10 (2023.02);
Abstract

3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.


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