The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

May. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yangsyu Lin, New Taipei, TW;

Chi-Lung Lee, New Taipei, TW;

Chien-Chi Tien, Hsinchu, TW;

Chiting Cheng, Taiching, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); G11C 11/419 (2006.01); H01L 23/522 (2006.01); G11C 11/412 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H10B 10/18 (2023.02); G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H10B 10/12 (2023.02);
Abstract

A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.


Find Patent Forward Citations

Loading…