The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Oct. 25, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/165 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7853 (2013.01); H01L 29/7854 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.