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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11854949 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Nov. 20, 2021

Package structure having a plurality of chips attached to a lead frame by redistribution layer

Applicant:

Jcet Group Co., Ltd., Wuxi, CN;

Inventors:

Yaojian Lin, Wuxi, CN;

Danfeng Yang, Wuxi, CN;

Shuo Liu, Wuxi, CN;

Chenye He, Wuxi, CN;

Assignee:

JCET GROUP CO., LTD., Wuxi, CN;

Attorney:

Cheng-Ju Chiang

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49534 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 23/3135 (2013.01); H01L 23/34 (2013.01); H01L 23/4952 (2013.01); H01L 24/24 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 2224/97 (2013.01); H01L 2924/181 (2013.01);
Abstract

The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

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