The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Jul. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Lien Huang, Jhubei, TW;

Guan-Ren Wang, Hsinchu, TW;

Ching-Feng Fu, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28556 (2013.01); H01L 21/02074 (2013.01); H01L 21/4828 (2013.01);
Abstract

An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.


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