The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Dec. 28, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kiyoshi Nakai, Kanagawa, JP;

Seiji Narui, Kanagawa, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); H01L 25/065 (2023.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.


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