The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Nov. 22, 2021
Achronix Semiconductor Corporation, Santa Clara, CA (US);
Michael Riepe, San Jose, CA (US);
Kamal Choundhary, Santa Clara, CA (US);
Amit Singh, San Jose, CA (US);
Shirish Jawale, San Jose, CA (US);
Karl Koehler, Fremont, CA (US);
Simon Longcroft, London, GB;
Scott Senst, Walker, MN (US);
Clark Hilbert, San Jose, CA (US);
Kent Orthner, Santa Cruz, CA (US);
Achronix Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.